1. Field of the Invention
The present invention generally relates to managing interrupt requests in programmable chip systems. More specifically, the invention relates to apparatus and methods for assigning interrupts in multi-master programmable chip systems.
2. Description of the Prior Art
A programmable chip system often includes master and slave components. A master component such as a processor typically initiates requests to slave components such as timers and parallel input/output (PIO) interfaces for data. In some cases, slave components may also initiate requests to master components. For instance, a slave component may generate and send an interrupt request to the master component.
Conventional programmable chip systems incorporate buses that often limit the number of master components that coexists in the system. However, some programmable chip systems offer mechanisms that allow multiple master components to operate efficiently. Systems that include multiple master components are referred to herein as multi-master systems. As the number of master components increases in multi-master systems, the task of assigning interrupt request numbers to particular slave and master component combinations becomes more challenging. Although there have been several approaches used to address this issue, more improvements to the assignment of interrupt requests in multi-master systems are needed.
In view of the foregoing, a system specifically designed to provide effective management of interrupt requests in multi-master systems would be highly beneficial.